Power semiconductors, in particular for higher voltage applications, require precise control of wafer thickness to reduce losses. When a power transistor is on, the difference between the drain (collector) voltage and the source (emitter) voltage of the transistor is only a few Volts. However, the difference between the drain and source connections jumps to multiples of 100 V or even multiples of 1,000 V during the blocking (off) state. The corresponding blocking voltage of the power transistor, which enables the transistor to withstand high off-state voltages, can be reduced depending on the thickness of the semiconductor material in the space-charge zone of the transistor. Some applications such as control functions are required to cope with this variable potential difference.
For example, level-shift transistors can be used to transmit in an arrangement of semiconductors a control signal with two power circuit switches from the control circuit at the lower switch on the source to the gate of the upper transistor. The gate of the upper transistor is related to the variable potential of the middle tap of the half-bridge and responds to this potential. Until recently, external semiconductor circuits were required. The external circuits must be equipped with a high isolation strength, such as for example optical couplers, transformers or special control switches on an SOI base material. Diodes have also been used which are coupled from a drift control zone of a TEDFET (trench extended drain field effect transistor) to the drain. The drift control zone controls the conducting channel in the drift zone when the transistor is driven in the on state (i.e. switched on). However, in each case a vertical integration of the power circuit switch has not been realized to date.